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Rev 1; 6/04
2-Wire, 5-Bit DAC with Three Digital Outputs
General Description
The DS4302 is a 5-bit digital-to-analog converter (DAC) with three programmable digital outputs. The DS4302 communicates through a 2-wire, SMBusTM-compatible, serial interface. The tiny 8-pin SOP package is ideal for use in space-constrained applications.
Features
SO Package is a Drop-In Replacement for the MPS1251 and MPS1252 Single 5-Bit DAC (32 Steps) 0V to 2V and 0V to 1.9V Versions Three Programmable Digital Outputs SMBus-Compatible Serial Interface 4.5V to 5.5V Supply Voltage Range 8-Pin SO and 8-Pin SOP Packages Industrial Temperature Range: -40C to +85C
DS4302
Applications
CCFL Backlight Brightness Control Power-Supply Calibration
PART DS4302Z-020 DS4302Z-019* DS4302U-020 DS4302U-019*
Ordering Information
VOUT RANGE 0V to 2.0V 0V to 1.9V 0V to 2.0V 0V to 1.9V TOP BRAND 4302B 4302A 4302B 4302A PINPACKAGE 8 SO 8 SO 8 SOP 8 SOP
Add "/T&R" for tape-and-reel orders. *Contact factory for availability.
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME SCL SDA VOUT GND P2 P1 P0 VCC Programmable Digital Output Power-Supply Input
GND 4
Pin Configuration
TOP VIEW
SCL SDA VOUT 1 2 8 7 VCC P0 P1 P2
FUNCTION Serial Clock Input. 2-wire clock input. Serial Data Input/Output. Bidirectional, 2-wire data pin. DAC Output Voltage Ground
DS4302
3 6 5
SO/SOP
SMBus is a trademark of Intel Corp.
______________________________________________ Maxim Integrated Products
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2-Wire, 5-Bit DAC with Three Digital Outputs DS4302
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC, SDA, and SCL Pins Relative to Ground.............................................-0.5V to +6.0V Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature.....See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C)
PARAMETER Supply Voltage Input Logic 1 (SDA, SCL) Input Logic 0 (SDA, SCL) SYMBOL VCC VIH VIL (Note 1) CONDITIONS MIN 4.5 2.0 GND - 0.3 TYP MAX 5.5 VCC + 0.3 0.8 UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = +4.5V to 5.5V, TA = -40C to +85C.)
PARAMETER Standby Current Input Leakage SDA Low-Level Output Voltage P0, P1, P2 Low-Level Output Voltage P0, P1, P2 High-Level Output Voltage VOUT Maximum Level (-020) VOUT Minimum Level (-020) VOUT Maximum Level (-019) VOUT Minimum Level (-019) Power-On Reset Settling Time D/A Output Levels SYMBOL ISTBY IL VOL1 VOL2 VOH (Notes 2, 3) (Note 4) 3mA sink current 6mA sink current (Note 1) 4mA sink (Note 1) 4mA source VCC = 5.0V, Data = 00000XXX (Note 3) VCC = 5.0V, Data = 11111XXX VCC = 5.0V, Data = 00000XXX (Note 3) VCC = 5.0V, Data = 11111XXX VCC - 0.4V 1.925 0.0 1.825 0.0 2.0 0.05 1.9 0.05 1.7 10 32 2.075 0.1 1.975 0.1 -1.0 0.0 0.0 CONDITIONS MIN TYP 200 MAX 300 +1.0 0.4 0.6 +0.4V UNITS A A V V V V V V V V s steps
X = Don't care.
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2-Wire, 5-Bit DAC with Three Digital Outputs
AC ELECTRICAL CHARACTERISTICS (Figure 3)
(VCC = +4.5V to 5.5V, TA = -40C to +85C, timing referenced to VIL(MAX) and VIH(MIN).)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Low Period of SCL High Period of SCL Data Hold Time Data Setup Time Start Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Setup Time SDA and SCL Capacitive Loading SYMBOL fSCL tBUF tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB (Note 5) (Note 5) (Note 5) CONDITIONS MIN 0 1.3 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 300 300 0.9 TYP MAX 400 UNITS kHz s s s s ns s ns ns s pF
DS4302
Note 1: Note 2: Note 3: Note 4:
All voltages referenced to ground. ISTBY specified for the inactive state measured with SDA = SCL = VCC and with VOUT, P0, P1, and P2 floating. No load on VOUT. The DS4302 will not obstruct the SDA and SCL lines if VCC is switched off as long as the voltages applied to these inputs does not violate their min and max input-voltage levels. Note 5: CB--total capacitance of one bus line in picofarads.
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2-Wire, 5-Bit DAC with Three Digital Outputs DS4302
Typical Operating Characteristics
(VCC = +5.0V, TA = +25C.)
STANDBY SUPPLY CURRENT vs. SUPPLY VOLTGE
DS4302 toc01
STANDBY SUPPLY CURRENT vs. TEMPERATURE
DS4302 toc02
SUPPLY CURRENT vs. SCL FREQUENCY
OUTPUTS UNLOADED SDA = VCC
DS4302 toc03
300 STANDBY SUPPLY CURRENT (A) 250 200 150 100 50 0 4.50 4.75 5.00 5.25 OUTPUTS UNLOADED SDA = SCL = VCC
300 STANDBY SUPPLY CURRENT (A) 250 200 150 100 50 0 OUTPUTS UNLOADED SDA = SCL = VCC = 5.0V
300 250 SUPPLY CURRENT (A) 200 150 100 50 0
5.50
-40
-20
0
20
40
60
80
0
100
200
300
400
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SCL FREQUENCY (kHz)
VOUT vs. DAC SETTING
DS4302 toc04
VOUT vs. SUPPLY VOLTAGE
VCC = SDA = SCL 2.05
DS4302 toc05
VOUT PERCENT CHANGE FROM +25C vs. TEMPERATURE
VCC = SDA = SCL VOUT PERCENT CHANGE (%) 0.5
DS4302 toc06
2.10
1.0
2.0
DS4302-020 VERSION
1.5 VOUT (V) VOUT (V) 2.00
0
1.0
0.5
1.95
-0.5
0 0 5 10 15 20 25 30 DAC SETTING (dec)
1.90 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V)
-1.0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
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2-Wire, 5-Bit DAC with Three Digital Outputs
Functional Diagram
DS4302
DATA BYTE REGISTER SDA SCL 2-WIRE INTERFACE MSB DAC VALUE P2 P1 P0 LSB OUTPUT CELL VCC
P0 VOUT 5-BIT DAC BUFFER
VCC VCC GND
OUTPUT CELL P1
OUTPUT CELL BANDGAP REFERENCE P2
DS4302
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2-Wire, 5-Bit DAC with Three Digital Outputs DS4302
DATA BYTE DAC VALUE MSB P2 P1 P0
5-bit DAC to adjust the voltage on VOUT and set the level of the three output pins: P0, P1, and P2. The read operation is used to recall the programmed settings.
2-Wire Definitions
The following terminology is commonly used to describe 2-wire data transfers. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, START, and STOP conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle, it initiates a low-power mode for slave devices. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 3 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 3 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (see Figure 3). Data is shifted into the device during the rising edge of the SCL.
Figure 1. Data Byte Configuration
Detailed Description
The DS4302 contains a 5-bit DAC and three programmable digital outputs. The DAC setting and the programmed output levels are contained in a 1-byte data word that defaults to 00h on power-up (see Figure 1 for data byte configuration). The upper 5 MSbits of the byte set the DAC and control the voltage produced on VOUT. A setting of 1111 1XXX sets the minimum output voltage from the DAC while a setting of 0000 0XXX sets the maximum output voltage from the DAC. The three LSbits of the data byte control the three output pins, P0, P1, and P2. Setting any of these control bits to a 0 pulls the corresponding outputs low and setting the bits to a 1 pulls the outputs high. The DS4302 communicates through a 2-wire (SMBuscompatible) digital interface and has a 2-wire address of 58h. Write and read operations are used to access the DAC and output settings. Each operation begins with a 2-wire START condition, consists of three bytes, and ends with a 2-wire STOP condition (see Figure 2). Using the write operation, the 2-wire master can program the
COMMUNICATIONS KEY S START A ACK WHITE BOXES INDICATE THE MASTER IS CONTROLLING SDA SHADED BOXES INDICATE THE SLAVE IS CONTROLLING SDA XXX X 8-BITS ADDRESS OR DATA NOTES: 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. 2) THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT.
P
STOP
XXX
X
WRITE A SINGLE BYTE S 0 1 0 1 1
58h 0 0 0 A 1 0 1
AAh 0 00h 0 1 A 0 0 0 0 0 0 0 0 A DATA BYTE A P 1 0 1 0 A DATA BYTE A P
READ A SINGLE BYTE S 0 1 0 1 1
59h 0
Figure 2. 2-Wire Communication Examples
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2-Wire, 5-Bit DAC with Three Digital Outputs DS4302
SDA tBUF
tLOW tR tF
tHD:STA
tSP
SCL
tHD:STA
tHIGH
tSU:STA tSU:DAT tSU:STO
STOP
START
tHD:DAT
REPEATED START
NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN).
Figure 3. 2-Wire Timing Diagram
Bit Read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup time (see Figure 3) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK): An Acknowledgement (ACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. For timing, see Figure 3. An ACK is the acknowledgement that the device is properly receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must ACK the last byte read to terminated communication so the slave returns control of SDA to the master.
7-BIT SLAVE ADDRESS 0 1 0 1 1 0 0 R/W DETERMINES READ OR WRITE
MOST SIGNIFICANT BIT
Figure 4. Slave Address and the R/W Bit
Slave Address and the R/W Bit: Each slave on the 2-wire bus responds to a slave addressing byte sent immediately following a START condition. The slave address byte contains the slave address and the R/W bit. The slave address (see Figure 4) is the most significant 7 bits and the R/W bit is the least significant bit. The DS4302's slave address is 0101100X (binary), where X is the R/W bit. If the R/W bit is zero (01011000), the master will write data to the slave. If the R/W is a one (01011001), the master will read data from the slave. Memory Address: During a 2-wire write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is the second byte transmitted during a write or read operation following the slave address byte (R/W=0). For a write operation, the memory address is 10101010 (AAh) and for a read operation, the memory address is 00000000 (00h).
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2-Wire, 5-Bit DAC with Three Digital Outputs DS4302
2-Wire Communication
Writing to a Slave: The master must generate a START condition, write the slave address (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave's acknowledgement during all byte-write operations. See Figure 2 for the write command example. Reading from a Slave: To read from the slave, the master generates a START condition, writes the slave address with R/W = 1, receives an ACK from the slave, reads a memory address of 00h from the slave, sends an ACK to the slave, reads the data byte, then sends an ACK to indicate the end of the transfer, and generates a STOP condition. See Figure 2 for the read command example.
Chip Information
TRANSISTOR COUNT: 2428 SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Application Information
Power-Supply Decoupling
To achieve the best results when using the DS4302, decouple the power supply with a 0.01F or a 0.1F capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins of the DS4302 to minimize lead inductance.
SDA and SCL Pullup Resistors
Pullup resistor values for SDA and SCL should be chosen to ensure that the rise and fall times listed in the AC electrical characteristics are within specification.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
DALLAS is a registered trademark of Dallas Semiconductor Corporation.

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